`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:32:22 04/26/2013
// Design Name:   system
// Module Name:   C:/ASU/CSE320/Project3/tb_system.v
// Project Name:  Project3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: system
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_system;

	// Inputs
	reg reset_b;
	reg go_btn;
	reg load_btn;
	reg sys_clk;
	reg [7:0] byte_in;

	// Outputs
	wire dp_dis;
	wire full;
	wire fifo_empty;
	wire [3:0] dis_control;
	wire [6:0] seg_data_out;

	// Instantiate the Unit Under Test (UUT)
	system uut (
		.reset_b(reset_b), 
		.go_btn(go_btn), 
		.load_btn(load_btn), 
		.sys_clk(sys_clk), 
		.byte_in(byte_in), 
		.dp_dis(dp_dis), 
		.full(full), 
		.fifo_empty(fifo_empty), 
		.dis_control(dis_control), 
		.seg_data_out(seg_data_out)
	);
	
	initial begin
		forever #5 sys_clk = ~sys_clk;
		
	end
	
	initial begin
		// Initialize Inputs
		reset_b = 1;
		go_btn = 0;
		load_btn = 0;
		sys_clk = 0;
		byte_in = 0;
		
		// Wait 100 ns for global reset to finish
		#20;
		
		
		reset_b = 0;
			#50
			//LDR A,1
			byte_in = 8'h01;
			#30
			load_btn = 1;
			#100
			load_btn = 0;
			#60
			//LDR B,2
			byte_in = 8'h12;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			//MUL C,A,B
			#50
			byte_in = 8'b1010_0001;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			#50
			//LDR D,1;
			byte_in = 8'b0011_0001;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			#50
			//ADD D,D,A
			byte_in = 8'b0111_1100;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			#50			
			//ADD D,D,A
			byte_in = 8'b0111_1100;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			#50
			//CMP A,C,D
			byte_in = 8'b11_00_10_11;
			#30
			load_btn = 1;
			#60
			load_btn = 0;
			#50
			go_btn = 1;
			#60
			go_btn = 0;
			#50;
			#1000;
	
				
		
		// Add stimulus here
		
	end
      
endmodule

